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Course
Highlights
This Application Workshop provides a thorough background in the use and application of the VHDL modeling and FPGA prototyping to the digital hardware design. This total training package covers all aspects of the VHDL language and FPGA platform. In terms of VHDL, we go from basic concepts and syntax, through synthesis coding styles and guidelines, to design verification. In terms of FPGA, we introduce the FPGA architectures, EDA flow, global and path specific timing constraints, digital clock manager and IP core reuse. The Workshop concludes with a project which requires you to apply all the knowledge you have learned in the 3 days.
Prerequisites
Delegates should have a basic knowledge of digital hardware design and be familiar with their choice of operating system. Although some experience of a software language is useful, it is not essential. The workshop assumes no prior knowledge of VHDL and FPGA.
Course Outline
Day 1: VHDL and FPGA Basics
Introduction to Digital System Design
- Platforms
- Hardware modeling overview
- Design flows
VHDL language introduction
- Design units and main language concepts
- Logical and relational operators, -concatenation and array slices
Design organization and management
- Options and strategies for using configurations
- File Compilation, elaboration, initialization -and simulation
- Efficient use of packages
FPGA architecture and EDA
- FPGA logic blocks
- FPGA routing networks
- State-of-the-art FPGA architectures
- FPGA EDA algorithms and methodology
FPGA tool Reports and global timing constraints
Day 2: VHDL and FPGA in Depth
Processes and sequential statements
Concurrent statements and equivalent processes
Simulation execution, sensitivity lists and wait statements
Variables and variable use
Arithmetical operators, overloading and arithmetic packages
RTL coding styles and guidelines for efficient synthesis
- Describing combinatorial logic
- Inferring registered logic
Coding styles for efficient hardware synthesis
Synthesis of variables
Modeling timing in VHDL
Delay modeling, gate level simulation and VITAL
Unconstrained, type indexed and multi-dimensional arrays
Types, sub-types, closely-related types and type conversions
FPGA digital clock manager
FPGA IP core reuse with CORE Generator
FPGA editor Demo
Day 3: Advanced VHDL and FPGA with a Project
FSM’s and state vector encoding
FSM coding styles and templates
Coding styles for testbenches, RTL and behavioral code
Coding styles and strategies for generating test stimulus
Creating clocks and resets
- Reading and writing data using file I/O
- Script driven testbenches
- Data and message outputs for efficient verification
- Result visualization
FPGA path-specific timing constraints
A project that requires both VHDL modeling and FPGA prototyping
Lab Descriptions
The labs have been designed to complement the lecture contents of the workshop. The last lab is a design project that needs you to use all the knowledge that you have learned in the workshop. The first few labs get you familiar with the tools you are using and the basic steps involved in simulating, synthesizing and implementing a small design. Subsequent labs are based upon design modeling, verification issues and performance tuning that are typically encountered in a real world design project.
Includes:
- Familiarization with simulation and synthesis tools
- Describing and verifying combinatorial logic
- Structural design and hierarchy
- Xilinx ISE and ModelSim tool flow
- Viewing FPGA architectures with the FPGA Editor
- Adding global timing constraints to designs
- Creating registered logic
- Designing with digital clock managers
- Using CORE Generator for IP reuse
- State machine design
- Verification using file I/O based testbenches
- VHDL modeling and FPGA prototyping of a traffic control system.
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