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Course
Description
This is a 2 day course to learn how to synthesize an algorithm written in MATLAB into a design that is optimized for a Xilinx FPGA. Learn how to take MATLAB coding changes that improve area and performance. Use the floating- to fixed-point and design exploration features of the AccelDSP Synthesis Tool to achieve maximum results. Learn how to merge a synthesized MATLAB block into a larger HDL design or System Generator design.
Duration
2 days
Course Outline
Module 1 : Introducing AccelDSP
Lab 1 – Get Started
Module 2: Synthesizable MATLAB
Lab 2 – Synthesizable MATLAB
Module 3: Quantization
Lab 3 – Quantization
Module 4: Multi-Rate Design
Lab 4 – Multi-Rate Design
Module 5: Using AccelWare
Lab 5 – Using AccelWare
Module 6: Design Exploration
Lab 6 – Design Exploration
Module 7: Adding Hardware Control
Lab 7 – Adding Hardware Control
Module 8: Coding for Hardware Performance
Lab 8 – Coding for Hardware Performance
Module 9: Interfacing to System Hardware
Lab 9 – Interfacing to System Hardware
Module 10: Exporting to System Generator
Lab 10 – Exporting to System Generator
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