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Course
Description
This 2-day comprehensive hands-on workshop is specially designed for designers new to CPLDS design or programmable logic. Beginning with the architecture of the Xilinx CoolRunner™-II CPLD, the workshop will provide the essential knowledge required to perform your own CPLD development. The first day of the workshop will take you from an introduction to Programmable Logic to optimizing designs to take full advantage of the architectural features of the CoolRunner™-II architecture. The second day of the workshop shall focus on how to create more
efficient designs to enhance performance. You will learn how to access hidden files to assist the fitting of designs and design making best possible use of Xilinx CPLD architectures. Plus, you will configure your personal CPLD evaluation board using Xilinx in-system-configuration software, which you may take with you after the workshop. Ultimately, the workshop objective is to groom you into a CPLD design Expert.
Duration
2 days
Prerequisites
Digital Designers who have working knowledge of basic HDL (VHDL or Verilog) and who are new to Xilinx CPLDs and/or ISE Tools.
Course Benefits
- Learn important design practices to ensure the best and most stable CPLD design
- Learn how to save costs by fitting designs into smaller devices
- Reduce time to market by learning how to use the ISE –series software to maximize design performance
- Increase your productivity by learning about advanced settings
Why
this training pays huge dividends
After completing this training, you will be able to:
- Describe the CPLD tool flow: Design Entry, Synthesis, Implementation, and Programming
- Understand what products Xilinx offers and where the CoolRunner-II CPLD fits into this offering
- Recognize the basic architectural resources of the CoolRunner-II CPLD
- Explain the ways in which the CoolRunner-II architecture helps to save power
- Fit difficult designs using the ISE Project Navigator
- Use the timing reports and Timing Analyzer to verify design performance
- Understand important Dos and Don’ts of designing with Xilinx CPLDs
Course Outline
Day 1
- Course Agenda
- CoolRunner-II CPLD Architecture
- CPLD Software Flow
- Lab 1: Xilinx CPLD Tool Flow
- Reading CPLD Reports
- Global Constraints
- Lab 2: Constraints for CPLDs
- CPLD Software Options
- Lab 3: CPLD Implementation Options
Day 2
- CPLD Software Flow
- CPLD Synthesis
- Advanced Fitting
- Lab 4: Fitting Difficult Designs Lab
- CPLD Timing
- Lab 5: CPLD Timing Lab
- CPLD Logic Engine
- CPLD Design Techniques
- Efficient Coding Practice
- Power Estimation
- Summary
Lab Descriptions
- Lab 1 - Xilinx CPLD Tool Flow: Create a new project in the Project Navigator of the ISE software. Implement a design by using default software options and configure the CoolRunner-II CPLD demo board with iMPACT, the Xilinx In-System Programming (ISP) software.
- Lab 2 - Constraints for CPLDs: Use constraints to specify clock frequencies, pin locations, and I/O standards for the CPLD demo board project. Fit the design and analyze the Timing and Fitter Reports to confirm performance and I/O placement.
- Lab 3 - Implementation Options: Implement the design with default software options and evaluate the design performance versus design requirements. Apply a global timing constraint for PERIOD to the design. Change the software options and add I/O constraints to meet the design's timing goals.
- Lab 4 – Fitting Difficult Designs: Apply the knowledge and techniques learned in the previous modules to fit designs into smaller devices.
- Lab 5 – CPLD Timing: Analyse the timing of a design and create test benches that can be simulated to verify the behavior of the design.
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