| Course
Description
This course allows you to explore the System Generator tool and to gain the expertise you need to develop advanced, low-cost Digital Signal Processing designs. This intermediate course in implementing DSP functions focuses on learning how to use System Generator for DSP, design implementation tools, and hardware co-simulation verification. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification by using Xilinx FPGA capabilities.
Level
- Intermediate
Duration
- 2 days
Who
Must Attend
System engineers, system designers, logic designers, and experienced hardware engineers interested in DSP design training who are implementing DSP algorithms using the MathWorks MATLAB® and Simulink® software and want to use Xilinx System Generator for DSP design
Software Tools
- Xilinx ISE Design Suite: System Edition 13.1
- MATLAB with Simulink software R2010b
Hardware
- Architecture: Spartan®-6 and Virtex®-6 FPGAs*
- Demo board: Spartan-6 FPGA SP605 or Virtex-6 FPGA ML605 board*
Prerequisites
- Experience with MATLAB and Simulink
- Basic understanding of sampling theory
Why
this training pays huge dividends
After completing this training, you will be able to:
- Describe the System Generator design flow for implementing DSP functions
- Identify Xilinx FPGA capabilities and implement a design from algorithm concept to hardware simulation
- List various low-level and high-level functional blocks available in System Generator
- Identify the high-level blocks available for FIR and FFT designs
- Design a multiple-clock-based System Generator system
- Embed two System Generator designs into a larger design
- Use a custom-designed FPGA PCB as a hardware co-simulation target
Course Outline
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Day 1
- Introduction to System Generator
- Simulink Software Basics
- Lab 1: Using the Simulink Software
- Basic Xilinx Design Capture
- Lab 2: Getting Started with Xilinx System Generator
- Signal Routing
- Lab 3: Signal Routing
- Implementing System Control
- Lab 4: Implementing System Control
Day 2
- Multi-Rate Systems
- Lab 5: Designing a MAC-based FIR
- Filter Design
- Lab 6: Designing a FIR Filter Using the FIR Compiler Block
- System Generator, Project Navigator, and Platform Studio Integration
- Lab 7: System Generator and Project Navigator Integration
- Spartan-6 and Virtex-6 FPGA DSP Platforms
- Lab 8: Using System Generator to Develop Virtex-6 and Spartan-6 FPGA DSP Applications
Lab Descriptions
- Lab 1: Using Simulink – Learn how to use Simulink toolbox blocks and design a system. Understand the effect sampling rate.
- Lab 2: Getting Started with Xilinx System Generator – Illustrates a DSP48-based design. Perform hardware co-simulation verification targeting a Xilinx evaluation board.
- Lab 3: Signal Routing – Design padding and unpadding logic by using signal routing blocks.
- Lab 4: Implementing System Control – Design an address generator circuit by using blocks and Mcode.
- Lab 5: Designing a MAC-based FIR – Using a bottom-up approach, design a MAC-based bandpass FIR filter and verify through hardware co-simulation by using a Xilinx evaluation board.
- Lab 6: Designing a FIR Filter Using the FIR Compiler Block or DAFIR Block – Design a bandpass FIR filter by using the FIR Compiler block to demonstrate increased productivity. Verify the design through hardware co-simulation by using a Xilinx evaluation board.
- Lab 7: System Generator and Project Navigator Integration – Learn how to embed two System Generator designs into a larger design and how VHDL created by System Generator can be incorporated into the simulation model of the overall system.
- Lab 8: Using System Generator to Develop Virtex-6 and Spartan-6 FPGA DSP Applications – Using System Generator to Develop Virtex-6 and Spartan-6 FPGA DSP Applications – Design a single-carrier Digital Up Converter (DUC) and Digital Down Converter (DDC) to meet WCDMA UTMS 3GPP specifications.
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