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Description
This course allows you to explore the System Generator tool and to gain the expertise you need to develop advanced, low-cost DSP designs. This intermediate course in implementing DSP functions focuses on learning how to use System Generator for DSP, design implementation tools, and hardware-in-the-loop verification. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification by using Xilinx FPGA capabilities.
Level
- Intermediate
Duration
- 2 days
Who
Must Attend
System engineers, system designers, logic designers, and experienced hardware engineers who are implementing DSP algorithms using The MathWorks MATLAB and Simulink and want to use Xilinx System Generator for DSP design
Prerequisites
- Experience with MATLAB and Simulink
- Basic understanding of sampling theory
Why
this training pays huge dividends
After completing this training, you will be able to:
- Describe the System Generator design flow for implementing DSP functions
- Identify Xilinx FPGA capabilities and implement a design from algorithm concept to hardware simulation
- List various low-level and high-level functional blocks available in System Generator
- Recognize that hardware may be required for high-level abstraction
- Identify the high-level blocks available for filter design
- Perform hardware-in-the-loop and improve productivity
- Design a multiple clock-based System Generator system
- Employ various design techniques for improving system performance
Course Outline
- Introduction to System Generator
- Simulink Basics
- Lab 1: Using Simulink
- Basic Xilinx Design Capture
- Lab 2: Getting Started with Xilinx System Generator
- Signal Routing
- Lab 3: Signal Routing
- Implementing System Control
- Lab 4: Implementing System Control
- Multi-Rate Systems
- Lab 5: Designing a MAC-based FIR Using the DSP48 Slice
- Filter Design
- Lab 6: Designing a FIR Filter Using the FIR Compiler Block
- Interfacing to System Hardware
- Lab 7: Designing interface to System Hardware
Lab Descriptions
- Lab 1: Using Simulink – Learn how to use Simulink toolbox blocks and design a system. Understand the effect sampling rate.
- Lab 2: Getting Started with Xilinx System Generator – Design a DSP48-based (ML403) or Multiply and Accumulator block-based (SP3E) 12 x 8 MAC. Perform hardware-in-the-loop verification targeting an ML403 and/or Spartan™-3E FPGA starter board.
- Lab 3: Signal Routing – Design padding and unpadding logic using signal routing blocks.
- Lab 4: Implementing System Control – Design an address generator circuit using blocks and Mcode.
- Lab 5: Designing a MAC-based FIR – Using a bottom-up approach, design a MAC-based bandpass FIR filter and verify through hardware-in-the-loop using an ML403 and/or Spartan-3E FPGA starter board.
- Lab 6: Designing a FIR Filter Using the FIR Compiler Block or DAFIR Block – Design a bandpass FIR filter using the FIR Compiler block (ML403) or DAFIR block (SP3E) to demonstrate increased productivity. Verify the design through hardware-in-the-loop using an ML403 and/or Spartan-3E FPGA starter board.
- Lab 7: Designing interface to System Hardware – Learn to use interfacing multiple System Generator modules to System Hardware. Verify the design in hardware using an Spartan-3 FPGA starter board.
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