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Course
Description
Become acquainted with the various solutions that Xilinx offers for Ethernet connectivity. Learn the basics of the Ethernet standard, protocol, and OSI model while applying Xilinx solutions via hands-on laboratory exercises. Perform simulation to understand fundamental principles and obtain the knowledge to assess hardware design considerations and software development requirements.
Level
Intermediate
Duration
2 days
Who
Must Attend
Engineers who would like to come up to speed on utilizing the Ethernet connectivity solution that Xilinx offers both in the form of soft cores and hard IP should attend this course
Prerequisites
- Fundamentals of FPGA course
- C programming knowledge recommended
- Experience with Xilinx ISE™ and Embedded Development Kit (EDK) software tool
Software Tools
- Xilinx ISE 8.2i SP1 with IP update 1
- Mentor Graphics ModelSim PE 6.0
- EDK 8.2
Why
this training pays huge dividends
After completing this training, you will be able to:
- Identify Ethernet basics
- Utilize various Ethernet cores, used either in standalone mode or as a
- peripheral in a processor-based design
- Determine the appropriate core to use
- Develop software to drive the core and achieve desired functionality
- Integrate hard and soft IP into the Embedded Development Kit (EDK)
Course Outlines
Day 1
- Ethernet Basics
- Network Protocols, Ethernet Interfaces, and Hardware
- Lab 1: Analyzing Ethernet Frames
- Physical Layer
- LocalLink Interface
- Lab 2: VLAN and Jumbo Frames
- Xilinx EMAC Solutions
Day 2
- Lab 3: Implementation
- EMAC and EMAC Lite
- Lab 4: EMAC Peripheral in Loopback Mode
- GEMAC
- TEMAC
- Lab 5: TEMAC in Loopback Mode
- 10G EMAC
- Lab 6: Analyzing 10G EMAC Frames
Lab Descriptions
- Lab 1 - Analyzing Ethernet Frames: Understand components of Ethernet frames and how the packets flow. Analyze various packets and observe how the core reacts to MAC address changes.
- Lab 2 - VLAN and Jumbo Frames: Modify the configuration register to enable and observe the effects of VLAN and jumbo frames. Understand statistics vectors.
- Lab 3 - Implementation: Use CORE Generator™ software to generate a gigabit Ethernet core and then proceed with the implementation flow.
- Lab 4 - EMAC Peripheral in Loopback Mode: Use the EDK to instantiate and connect the OPB EMAC peripheral to the OPB bus. Develop software to place the core in loopback mode.
- Lab 5 - TEMAC in Loopback Mode: Use the EDK to instantiate a hard TEMAC and soft PLB TEMAC wrapper. Configure cores in scatter gather DMA mode. Use three programs to test the hardware in polled, simple DMA, and scatter gather DMA modes after placing the hardware in loopback mode.
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