FPGA Design Expert

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Course Description
This 3-day comprehensive hands-on workshop is specially designed for designers new to FPGAs design or programmable logic. Beginning with the architecture of Xilinx FPGA, the workshop will first provide the essential knowledge required to implement a design successfully using the ISE software tools. The first part of the workshop will give you a headstart on not just a fast design turn, but an elegant design as well. The second part of the workshop shall focus on how to create more efficient designs to enhance overall performance. You will learn how to create a faster design, fit your design into a smaller FPGA or a lower speed grade, thereby reducing your system cost and development time. Plus, you will configure your personal FPGA evaluation board using Xilinx in-systemconfiguration software, which you may take with you after the workshop. Ultimately, the workshop objective is to groom you into a FPGA Design Expert.

Duration
3 days

Prerequisites
Digital Designers who have working knowledge of basic HDL (VHDL or Verilog) and who are new to Xilinx FPGAs and/or ISE Tools.

Course Benefits

  • Learn important design practices to ensure the best and most stable FPGA design
  • Learn how to save costs by increasing your design utilization
  • Reduce time to market by learning how to use the ISE –series software to maximize design performance
  • Increase your productivity by learning about advanced settings

Why this training pays huge dividends
After completing this training, you will be able to:

  • Use Xilinx Project Navigator to iImplement an FPGA design
  • Create DCM instantiations with the Architecture Wizard
  • Assign pin locations with the PACE tool
  • Read reports to determine whether design goals were met
  • Use the Constraints Editor to assign pin locations and enter basic global timing constraints
  • Locate and modify implementation options
  • Describe a flow for obtaining timing closure
  • Describe architectural features of the Virtex™-4 FPGA
  • Describe the features of the Digital Clock Manager (DCM) and Phase-Matched Clock Divider (PMCD) and how they can be used to improve performance
  • Increase performance by duplicating registers and pipelining
  • Write HDL code by using a style that is optimal for targeting Xilinx devices
  • Describe different synthesis options and how they can improve performance
  • Create and integrate cores into your design flow by using the CORE Generator™ software system
  • Run behavioral simulation on an FPGA design that contains cores
  • Pinpoint design bottlenecks by using the Timing Analyzer reports
  • Apply advanced timing constraints to meet your performance goals
  • Use advanced implementation options to increase design performance

Course Outline

Day 1

  • Basic FPGA Architecture
  • Lab 1: Xilinx Tool Flow
  • Reading Reports
  • Lab 2: Architecture Wizard and PACE
  • Global Timing Constraints
  • Lab 3: Global Timing Constraints
  • Implementation Options
  • Lab 4: Implementation Options
  • Synchronous Design Techniques

Day 2

  • Review of Fundamentals of FPGA Design
  • Designing with Virtex-4 FPGA Resources
  • CORE Generator Software System
  • Lab 5: CORE Generator Software System
  • Designing Clock Resources
  • Lab 6: Designing Clock Resources
  • FPGA Design Techniques
  • Synthesis Techniques
  • Lab 7: Synthesis Techniques

Day 3

  • Achieving Timing Closure
  • Lab 8: Review of Global Timing Constraints
  • Timing Groups and OFFSET Constraints
  • Path-Specific Timing Constraints
  • Lab 9: Achieving Timing Closure
  • Advanced Implementation Options
  • Lab 10: Designing for Performance
  • Power Estimation (Optional)
  • Lab 11: FPGA Editor Demo (Optional)
  • ChipScope™ Pro Analyzer (Optional)
  • Lab 12: ChipScope Pro Analyzer (Optional)
  • Course Summary

Lab Descriptions

  • Lab 1 - Xilinx Tool Flow: Create a new project in the ISE Project Navigator and use the Architecture Wizard and PACE tool in the design process. Implement a design using default software options.
  • Lab 2 - Architecture Wizard and PACE: Use the Architecture Wizard to customize a DCM, incorporate the DCM into the design, use PACE to assign pin locations, and implement the design.
  • Lab 3 - Global Timing Constraints: Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place and Route Static Timing Report to determine the delay of the longest-constrained path for each timing constraint.
  • Lab 4 - Implementation Options: Adjust process properties and I/O configuration options to improve design performance.
  • Lab 5: CORE Generator Software System – Create a core, instantiate the core into VHDL or Verilog source code, and run behavioral simulation.
  • Lab 6: Designing Clock Resources – Use the Clocking Wizard to configure DCMs and global clock buffer resources.
  • Lab 7: Synthesis Techniques – Experiment with different synthesis options and view the results. Versions of this lab are available for Synplicity Synplify Pro, Precision RTL, and Xilinx XST software.
  • Lab 8: Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.
  • Lab 9: Achieving Timing Closure – Review timing reports and enter path-specific timing constraints to meet performance goals.
  • Lab 10: Designing for Performance – Improve performance and maximize results solely with implementation options.
  • Lab 11: FPGA Editor Demo – Use the FPGA Editor to view a design and add a probe to an internal net.
  • Lab 12: ChipScope Pro Analyzer – Add an internal logic analyzer to a design to perform real-time debugging