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Course
Description
Learn to increase design performance and achieve repeatable results by using the PlanAhead™ software tool. Topics include: a product overview, synthesis and project tips, design analysis, creating a floorplan, improving performance, experimenting with implementation options, incremental methodology, block-based IP design, and I/O pin assignment.
Level
Intermediate
Duration
2 days
Why
this training pays huge dividends
After completing this training, you will be able to:
- Import designs into the PlanAhead software project environment
- Analyze design statistics, connectivity, timing, and placement results
- Run the Design Rule Checker (DRC) and Weighted Average Simultaneous Switching Output (WASSO) analysis
- Partition and floorplan designs
- Run ExploreAhead to try multiple implementation strategies
- Import and analyze the implementation results to improve the floorplan
- Floorplan to improve performance and consistency
- Use block-based design and create and reuse module-level IP
- Use PinAhead to import, define and assign I/O pins for the design
Software Tools
Xilinx ISE
Course Outline
Day 1
- Course Overview
- Lab 1: Getting Started with PlanAhead
- Design Analysis and Exploration
- Lab 2: Design Analysis and Exploration
- Design Partitioning and Top-Level Floorplanning
- Lab 3: Design Partitioning and Top-Level Floorplanning
- Implementing a Floorplanned Design
- Lab 4: Implementation
Day 2
- Floorplanning Techniques
- Lab 5: Floorplanning
- Tuning a Floorplan for Performance
- Lab 6: Floorplan Tuning
- Block-Based Design and IP Reuse
- Lab 7: Block-Based Design and IP Reuse
- I/O Pin Assignment
- Lab 8: I/O Pin Assignment
- Floorplanning Strategies
- Course Summary
Lab Descriptions
- Lab 1: Getting Started with the PlanAhead Tool – Illustrates the steps you take to import a synthesized design into the PlanAhead tool so that you can begin floorplanning. Also introduces the PlanAhead tool environment and views.
- Lab 2: Assigning I/O Pins – Introduces the PinAhead environment for performing I/O pin assignment. You will create a project, import and export I/O ports lists, create I/O ports and interfaces, and make pin assignments.
- Lab 3: RTL Development and Analysis – Provides an overview of the RTL development and analysis environment. You will analyze the RTL logic hierarchy, RTL schematic, RTL resource estimations and run RTL Design Rule Check (DRCs).
- Lab 4: Implementing with the PlanAhead Tool – Illustrates a walkthrough of the front-to-back, RTL-to-bitstream design flow. You will run synthesis, import synthesis results, run implementation, and import and analyze the implementation.
- Lab 5: Design Analysis – Introduces the pre- and post-implementation design analysis features of the PlanAhead software.
- Lab 6: Floorplanning – Provides an introduction to some of the capabilities and benefits of using the PlanAhead tool for designing high-end FPGAs.
- Lab 7: Debugging with the ChipScope Tool – Provides an introduction to using the PlanAhead tool for debugging designs with the ChipScope™ Pro cores and tools.
- Lab 8: Using the PlanAhead Tool with Project Navigator – Illustrates some of the capabilities and benefits of using the PlanAhead tool integrated within the ISE software Project Navigator environment.
Prerequisites
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