Verilog & FPGA Design Expert

Course Description

Verilog & FPGA Design Expert is a comprehensive training package that comprises of 2 course modules: Comprehensive Verilog, and FPGA Design Expert . Based on Xilinx industry standard, this 6-day training package can be considered as the minimum training requirement for project readiness.

Comprehensive Verilog (3-day) is a thorough introduction to the Verilog language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall Verilog proficiency and enhance your FPGA optimization. This course covers Verilog 1995 and 2001.

FPGA Design Expert (3-day) is specially designed for designers new to FPGAs design or programmable logic. Beginning with the architecture of Xilinx FPGA, the workshop will first provide the essential knowledge required to implement a design successfully using the ISE software tools. The first part of the workshop will give you a headstart on not just a fast design turn, but an elegant design as well. The second part of the workshop shall focus on how to create more efficient designs to enhance overall performance. You will learn how to create a faster design, fit your design into a smaller FPGA or a lower speed grade, thereby reducing your system cost and development time. Plus, you can take home a Spartan 3E evaluation board using Xilinx in-systemconfiguration software. Ultimately, the workshop objective is to groom you into a FPGA Design Expert

Duration
6 days

Prerequisites
You are required to have basic digital design knowledge as well as at least two months' coding experience is recommended and have attended ‘Comprehensive VHDL’ course or equaivalent skills.

Why this training pays huge dividends
After completing this training, you will be able to:

Comprehensive Verilog

  • Write RTL Verilog code for synthesis
  • Write Verilog test fixtures for simulation
  • Create a Finite State Machine (FSM) by using Verilog
  • Target and optimize Xilinx FPGAs by using Verilog
  • Use enhanced Verilog file I/O capability
  • Run a timing simulation by using Xilinx Simprim libraries
  • Create and manage designs within the ISE software design environment
  • Download to the Spartan-6 FPGA SP605 demo board

FPGA Design Expert

  • Take advantage of the primary features of the Spartan®-6 FPGA
  • Use the Xilinx Project Navigator to implement and simulate an FPGA design
  • Read reports and determine whether your design goals were met
  • Use the Clocking Wizard to create DCM instantiations
  • Use the I/O Planner to make good pin assignments
  • Use the Xilinx Constraints Editor to enter global timing constraints
  • Describe the architectural features of the Virtex-6 FPGA and Spartan-6 FPGAs
  • Create and integrate cores into your design flow by using the CORE Generator™ software system
  • Describe the clocking features of the Virtex-6 and Spartan-6 FPGAs and how they can be used to improve performance
  • Increase performance by duplicating registers and pipelining
  • Increase system reliability by adding an appropriate synchronization circuit
  • Describe different synthesis options and how they can improve performance
  • Describe a flow for obtaining timing closure
  • Pinpoint design bottlenecks by using Timing Analyzer reports
  • Apply advanced timing constraints to meet your performance goals
  • Use advanced implementation options to increase design performance

Course Outline

Module 1: Comprehensive Verilog

Day 1

  • Hardware Modeling Overview
  • Verilog Language Concepts
  • Modules and Ports
  • Lab 1: Building Hierarchy
  • Introduction to Testbenches
  • Lab 2: Verilog Simulation and RTL Verification

Day 2

  • Verilog Operators and Expressions
  • Data Flow-Level Modeling
  • Lab 3: Memory
  • Verilog Procedural Statements
  • Lab 4: Clock Divider and Address Counter
  • Controlled Operation Statements
  • Lab 5: n-bit Binary Counter and RTL Verification

Day 3

  • Verilog Tasks and Functions
  • Advanced Language Concepts
  • Lab 6: Timing Simulation
  • Finite State Machines
  • Lab 7: Finite State Machines
  • Targeting Xilinx FPGAs
  • Lab 8: Implement and Download
  • Advanced Verilog Testbenches
  • Lab 9: Using Text I/O

Lab Descriptions
The labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. The labs are written, synthesized, behaviorally simulated, and implemented by the student. The focus of the labs is to write code that will optimally infer reliable and high-performance circuits. The labs culminate in a functional calculator that students verify in simulation.

Module 2: FPGA Design Expert


Day 4

  • Basic FPGA Architecture
  • Xilinx Tool Flow
  • Lab 1: Xilinx Tool Flow
  • Reading Reports
  • Lab 2: Clocking Wizard and Pin Assignment
  • Lab 3: Pre-Assigning I/O Pins Using the PlanAhead Tool
  • Global Timing Constraints
  • Lab 4: Global Timing Constraints
  • Synchronous Design Techniques
  • Course Summary

Day 5

  • Review of Essentials of FPGA Design
  • Designing with FPGA Resources
  • CORE Generator Software System
  • Basic FPGA Clock Resources
  • Virtex-6 and Spartan-6 FPGA Clock Resources
  • Lab 5: Designing with FPGA Resources
  • FPGA Design Techniques
  • Synthesis Techniques
  • Lab 6 : Synthesis Techniques

Day 6

  • Achieving Timing Closure
  • Lab 7 : Review of Global Timing Constraints
  • Path-Specific Timing Constraints, Part 1
  • Path-Specific Timing Constraints, Part 2
  • Lab 8 : Achieving Timing Closure
  • Advanced Implementation Options
  • Lab 9 : Designing for Performance
  • Lab 10 : FPGA Editor Demo (optional)
  • ChipScope Pro Software (optional)
  • Lab 11 : ChipScope Pro Software (optional)