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Course
Description
Interested in learning how to utilize Virtex™-5 FPGA architectural resources effectively? Targeted towards experienced Xilinx users who have already completed the course "FPGA Design Expert" and have a comprehensive knowledge of Virtex-4 FPGAs. This course focuses on understanding as well as designing into several of the new and enhanced resources found in our newest device.
Topics covered include a Virtex-5 FPGA overview, new LUT, DCM and PLL, global and regional clocking techniques, memory, DSP and arithmetic logic, and source-synchronous resources. A combination of modules and labs allow for practical hands-on application of the principles taught.
Level
- Intermediate
Duration
- 1 day
Why
this training pays huge dividends
After completing this training, you will be able to describe and utilize new Virtex-5 FPGA resources, including:
- 6-input LUT
- DCM and PLL
- Global and regional clock resources
- Memory resources
- Arithmetic and DSP resources
Software Tools
- Xilinx ISE 8.2i
- Synplicity Synplify Pro 8.2
- Mentor Graphics Precision 2005b
Course Outline
- Virtex-5 FPGA Overview
- Utilizing Virtex-5 FPGA Logic Resources
- 6-input LUT
- Memory
- DSP
- Configuration
- Clocking Resources
LAB DESCRIPTIONS
The labs will provide practical hands-on application of the principles taught throughout the course.
Who
Must Attend
For those who have taken the "FPGA Design Expert" course. A comprehensive knowledge of the Virtex-4 family architecture is also required. This material should be considered a Virtex-5 FPGA update course from the Virtex-4 FPGA family.
Prerequisites
- Attended "FPGA Design Expert" course
- Attended "Designing with the Virtex-4 Family" course
- Comprehensive knowledge of the Virtex-4 FPGA
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